Bipolar memory circuit

ABSTRACT

A bipolar memory circuit is provided with a delay circuit which receives a write enabling signal, a gate circuit which detects the coincidence between an input signal and an output signal of the delay circuit, and a circuit which is started by an output signal of the gate circuit and which provides a pulse signal of a fixed time. The operation of a write driver circuit in the bipolar memory circuit is controlled by the pulse signal. Noise interfering in the write enabling signal are neglected by the use of the delay circuit and the gate circuit. The pulse width of the write enabling signal is permitted to be made smaller than the pulse width of the pulse signal required by the write driver circuit.

BACKGROUND OF THE INVENTION

This invention relates to a bipolar memory circuit which has currentswitching type memory cells.

In the bipolar memory circuit having the current switching type memorycells, the distinction between the read cycle and write cycle ofinformation is determined in accordance with the level of a writeenabling signal which is externally supplied.

The bipolar memory circuit can therefore cause a malfunction in responseto the interference of a noise in the write enabling signal in, forexample, a read cycle period.

In order to prevent the bipolar memory circuit from erroneouslyoperating in response to the noise etc., a method wherein a writeenabling signal and a signal obtained by delaying the write enablingsignal are logically combined and the resulting composite signal is usedas an input signal to a write driver circuit has been proposed asdisclosed in Japanese patent application Laid-open Publication which waspublished on Mar. 18, 1977, No. 52-35535. According to this method, anypulse noise to interfere in the write enabling signal as has a pulsewidth less than the signal delay time becomes negligible.

With the known method, however, the setup time becomes longer by thedelay time of the signal. Moreover, since the write time in the signalobtained by the logic combination decreases, the pulse width of thewrite enabling signal to be externally supplied must be increased. Withthe known method, accordingly, the write cycle period lengthens.

SUMMARY OF THE INVENTION

An object of this invention is to provide a bipolar memory circuit whichcan perform a high-speed and stable write operation.

Another object of this invention is to provide a bipolar memory circuitwhich can make the application timing margin of a write enabling signallarge.

Another object of this invention is to provide a bipolar memory circuitin which the fluctuations of a reference potential attributed to thechanges of the operating current of an information readout circuit aresmall.

Futher objects of this invention will become apparent from the followingdescription taken in conjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an embodiment of this invention,

FIG. 2 is a logic circuit diagram of a pulse generator according to thisinvention,

FIG. 3 is a concrete circuit diagram of a memory array,

FIG. 4 is a concrete circuit diagram of an output buffer circuit,

FIG. 5, including A-I, is an operating waveform diagram of the bipolarmemory circuit according to this invention,

FIG. 6 is a diagram of the write characteristic curves of the bipolarmemory circuit,

FIG. 7 is a logic circuit diagram of essential portions showing anotherembodiment of this invention, and

FIG. 8 is a circuit diagram of still another embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In accordance with this invention, there is disposed a pulse generatorwhich is started by a write enabling signal having a pulse width greaterthan a predetermined time as is externally supplied and which forms asignal of a pulse width being constant irrespective of thefirst-mentioned pulse width, and the output signal of the pulsegenerator is substantially made a write enabling signal for a memorycell.

Hereunder, this invention will be described in detail in connection withembodiments.

FIG. 1 is a block diagram of a bipolar memory circuit showing anembodiment of this invention.

Respective circuit blocks in the figure are formed on a singlesemiconductor substrate by known semiconductor integrated circuittechniques. Terminals A₀ to A₉, D_(OUT), CS, WE, D_(in), GND and V_(EE)are formed as external terminals a semiconductor integrated circuitdevice (IC).

Numeral 1 designates a memory array. It includes a plurality of currentswitching (emitter-coupled) type memory cells, a plurality of word linesW₁₁ to W₃₂₁ and a plurality of digit lines as will become apparent fromFIG. 3 later.

Numeral 2 designates an X address decoder. By receiving an addresssignal of a plurality of bits A₀ to A₄, it forms an X address selectsignal for selecting one of the plurality of word lines of the memoryarray 1.

Shown at 3 is a word driver. By receiving the output of the X addressdecoder 2, it forms a word line select signal for performing theselection of the word line.

Shown at 4 is a Y address decoder. By receiving an address signal of aplurality of bits A₅ to A₉, it forms Y address select signals Y₁ to Y₃₂for selecting the plurality of digit lines of the memory array.

Numeral 5 indicates a digit line selector circuit, which forms signalsfor selecting the plurality of digit lines of the memory array by theuse of the Y address select signals.

FIG. 3 shows concrete examples of the memory array 1, the X addressdecoder 2, the word driver 3 and the digit line selector circuit 5 inFIG. 1.

The memory array 1 is constructed of memory cells MS₁₁ to MS₂₂ in amatrix arrangement, word lines W₁₁ and W₂₁, lower word lines W₁₂ andW₂₂, holding current sources IR₁ and IR₂, and digit lines D₁ to D₄.

As the memory cell MS₁₁ is typically illustrated, each of the memorycells MS₁₁ to MS₂₂ is constructed of a pair of multiemitter transistorsQ₁ to Q₂ whose bases and collectors are cross-connected, and resistorsR₁ and R₂ and diodes D₁ and D₂ which are used as the collector loads ofthe transistors Q₁ and Q₂.

As shown in the figure, pluralities of memory cells arranged in the samerows are respectively connected in common to the word lines W₁₁ and W₂₁and the lower word lines W₁₂ and W₂₂. The holding current sources IR₁and IR₂ are connected between the lower word lines W₁₂ and W₂₂ and anegative voltage source terminal V_(EE).

Input and output terminals e₁ and e₃ of pluralities of memory cellsarranged in the same columns are respectively connected in common to thedigit lines D₁ to D₄ as shown in the figure.

The X address decoder 2 is constructed of address buffers BA₀ to BA₄ andNOR circuits 21' to 25'.

The address buffers BA₀ to BA₄ provide non-inverted signals at terminalsa₀ to a₄ and inverted signals at terminals a₀ to a₄ in response to theinput address signals which are supplied through the respectivelycorresponding external terminals A₀ to A₄.

Each of the NOR circuits 21' and 25' is constructed of transistors Q₃ toQ₄ whose bases selectively receive the output signals of the addressbuffers BA₀ to BA₄, a transistor Q₅ whose base receives an outputvoltage from a reference voltage source E₁, and resistors R₃ and R₄.

The word driver 3 is constructed of emitter follower circuits 31 to 35each of which includes an emitter follower transistor Q₆.

The digit line selector circuit 5 is constructed of a writing andreading circuit 51, a selector circuit 52 and a constant current circuit53.

The writing and reading circuit 51 includes transistors Q₇ to Q₁₀ whichare disposed in correspondence with the digit lines D₁ to D₄. Thetransistors Q₇ and Q₉ whose emitters are connected to one-side digitlines D₁ and D₃ in the respective pairs of digit lines D₁ and D₂, and D₃and D₄ have their collectors connected in common to a sense line S₁ andhave their bases connected in common to a write line W₁. Similarly, thetransistors Q₈ and Q₁₀ whose emitters are connected to the other-sidedigit lines D₂ and D₄ have their collectors connected in common to asense line S₂ pairing with the sense line S₁ and have their basesconnected in common to a write line W₀ pairing with the write line W₁.

The selector circuit 52 includes transistors Q₁₁ to Q₁₄ which aredisposed in correspondence with the digit lines D₁ to D₄. The bases ofthe transistors Q₁₁ and Q₁₂ corresponding to the pair of digit lines D₁and D₂ are supplied with the Y address select signal Y₁ of the Y addressdecoder 4, while the bases of the transistors Q₁₃ and Q₁₄ correspondingto the other pair of digit lines D₃ and D₄ are similarly supplied withthe Y address select signal Y₂.

The constant current circuit 53 is constructed of constant current meansIR₃ to IR₆ which are connected between the respective digit lines D₁ toD₄ and the negative voltage source terminal V_(EE).

The selection and non-selection of the memory cells in the memory array1 and the reading of information from the selected memory cell as wellas the writing of information into the selected memory cell aredetermined in accordance with the current switching operations amongthose transistors in the memory cells, the reading and writing circuit51 and the selector circuit 52 whose emitters are connected in common tothe digit lines.

The word line not to be selected is made a comparatively low potential(hereinbelow, termed "V_(L) "). In contrast, the word line to beselected is made a comparatively high potential (hereinbelow, termed"V_(H) ") so that the lower one of the collector potentials of the twotransistors Q₁ and Q₂ in the memory cell connected to this word line maybecome higher than the higher one of the collector potentials of the twotransistors Q₁ and Q₂ in the memory cells connected to the non-selectedword line.

The Y address select line not to be selected is made a high potential(hereinbelow, termed "V_(YH) ") which is somewhat higher than the V_(H),whereas the Y address select line to be selected is made a low potential(hereinbelow, termed "V_(YL) ") which is lower than the lower collectorpotential of the two transistors Q₁ and Q₂ in the memory cell connectedto the selected word line.

At reading, both the write lines W₁ and W₀ are made a referencepotential (hereinbelow, termed "V_(R) ") which is intermediate betweenthe collector potentials of the transistors Q₁ and Q₂ of the memory cellconnected to the selected word line. At writing, that one of the writelines W₁ and W₀ which has been selected in accordance with aninformation to be written is made a potential (hereinbelow, termed"L_(WL) ") which is lower than the lower one of the two collectorpotentials, while the other is made substantially the referencepotential V_(R).

In case where the Y address select line Y₁ is made the non-selectionlevel V_(YH), the transistors Q₁₁ and Q₁₂ of the selector circuit 52 arebrought into the "on" state by the high potential V_(YH) of the Yaddress select line Y₁, and the constant current means IR₃ and IR₄ aresupplied with currents from the transistors Q₁₁ and Q₁₂. In consequence,the emitters e₁ and e₃ connected to the digit lines D₁ and D₂ in thememory cells MS₁₁ and MS₂₁ are held in the "off" state. In this case,currents for holding information flow to the memory cells MS₁₁ l andMS₂₁ owing to the holding current means IR₁ and IR₂. At this time, thetransistors Q₇ and Q₈ of the reading and writing circuit 51 are alsoheld in the "off" state in correspondence with the "on" state of thetransistors Q₁₁ and Q₁₂.

When the word line W₁₁ is made the selection level V_(H) and the Yaddress select line Y₁ is made the selection level V_(YL), the memorycell MS₁₁ is selected. In this case, both the transistors Q₁₁ and Q₁₂ ofthe selector circuit 52 are brought into the "off" state by the currentswitching operation as described above.

Although this is not especially restrictive, "1" of stored informationin the memory cell is caused to correspond to the "on" state of thetransistor Q₁ and the "off" state of the transistor Q₂, and "0" iscaused to correspond to the "off" state of the transistor Q₁ and the"on" state of the transistor Q₂.

At the reading, if the information of the selected memory cell MS₁₁ is"1", the base potential of the transistor Q₁ of this memory cell MS₁₁ ismade a potential higher than the base potential V_(R) of the transistorQ₇. In consequence, current flows from the emitter e₁ of the transistorQ₁ to the constant current means IR₃. In contrast, the base potential ofthe transistor Q₁ is made a potential lower than the base potentialV_(R) of the transistor Q₈. In consequence, current flows from thetransistor Q₈ to the constant current source IR₄. The current throughthe transistor Q₈ gives rise to a voltage drop across a load resistor R₆connected to the sense line S₂. That is, in accordance with "1" beingthe stored information in the selected memory cell MS₁₁, the sense lineS₁ is made the high level and the sense line S₂ is made the low level.In contrast, if the stored information in the selected memory cell MS₁₁is "0", the sense line S₁ is made the low level and the sense line S₂ ismade the high level.

At the writing, in response to e.g. the high level of a data signalsupplied to the external terminal D_(in), the write line W₁ is made thelow potential V_(WL) and the write line W₀ is made the referencepotential V_(R). In this case, if the memory cell to be selected isMS₁₁, current is caused to flow from the emitter e₁ of the transistor Q₁of the memory cell MS₁₁ to the constant current means IR₃ by the currentswitching operation of this transistor Q₁ and the transistor Q₇irrespective of the previous "on" or "off" state of the transistor Q₁.As a result, the transistor Q₁ is brought into the "on" state, and "1"as an information is written into the memory cell MS₁₁.

Referring back to FIG. 1, symbols B₂ to B₄ designate input buffercircuits which receive the chip select signal CS, the write enablingsignal WE and the data input signal D_(in) externally applied to the IC,respectively.

An output signal of the buffer circuit B₂ is made inphase with the chipselect signal being the input, and is supplied to an output buffercircuit B₁ and gate circuits G₁ and G₂. In this embodiment, although nospecial restriction is intended, the chip or memory circuit is put intothe selected state by the low level of the chip select signal CS andinto the non-selected state by the high level thereof as will becomeapparent later.

The buffer circuit B₃ provides a signal WE' inphase with the writeenabling signal WE of the input as is supplied to a pulse generator 6 tobe described later, and an inphase signal WE which is supplied to thebuffer circuit B₁. The write enabling signal WE is made a low level whenan information is to be written into the memory cell, and is made a highlevel when an information is to be read out of the memory cell.

The buffer circuit B₄ provides a signal d_(in) antiphase to the inputdata signal D_(in) as is supplied to the gate circuit G₁, and an inphasesignal d_(in) which is supplied to the gate circuit G₂.

As shown in FIG. 2, the pulse generator 6 is constructed of a firstdelay circuit 7 which delays the write enabling signal WE' supplied fromthe buffer circuit B₃, a NOR gate circuit G₃ which receives a delayedsignal provided from the delay circuit 7 and the write enabling signalWE', a second delay circuit 8 which delays an output signal of the gatecircuit G₃, and a reset-preferential flip-flop circuit 9 whose set inputis the output of the gate circuit G₃ and whose reset input is an outputsignal of the second delay circuit 8. As will be elucidated later, theinverted output Q of the flip-flop circuit 9 is used as a write enablingsignal WE" which is applied to the gate circuits G₁ and G₂.

The gate circuit G₁ provides the write line W₁ with a write signal byreceiving the chip select signal CS through the input buffer circuit B₂,the write enabling signal WE through the pulse generator 6 and theinverted signal of the input data signal D_(in) through the buffercircuit B₄ as described above. The write signal on the write line W₁ ismade the low potential V_(WL) only when the write enabling signal WE"supplied from the pulse generator 6 is at the low level and besides theinput data signal D_(in) is at the high level in correspondence with "1"of the information, and it is made the reference potential V_(R) at anyother time, that is, when the write enabling signal WE" is at the highlevel or when the input data signal D_(in) is at the low level incorrespondence with "0" of the information.

The gate circuit G₂ has the same construction as that of the gatecircuit G₁ except that it receives the signal inphase with the inputdata signal D_(in) through the buffer circuit B₄. Accordingly, itsupplies a signal of the level of the low potential V_(WL) to the writeline W₀ only when the write enabling signal We" is at the low level andbesides the input data signal D_(in) is at the low level incorrespondence with "O" of the information, and it supplies a signal ofthe level of the intermediate potential V_(R) at any other time.

FIG. 5 shows a time chart of the bipolar memory circuit of the aboveconstruction.

The chip is put into the selected state in response to the fact that thechip select signal CS is made the low level at a time t₀ as shown at Ain FIG. 5.

As shown at B in FIG. 5, the address signal A_(i) is set into a statecorresponding to the memory cell to-be-selected at a time t₁. As shownat H in FIG. 5, the signal D_(OUT) corresponding to the information ofthe selected memory cell is provided at a time t₂ which is later thanthe time t₁ by a delay time determined by the various circuits describedabove.

In case of writing data, by way of example, the input data D_(in) asshown by a broken line at C in FIG. 5 is set at a time t₃, whereupon thewrite enabling signal WE to be applied to the external terminal isbrought from the previous high level to the low level as shown at D inFIG. 5 at a time t₄.

The NOR gate circuit G₃ in the pulse generator 6 receives the low levelsignals at its two input terminals when the period of time during whichthe write enabling signal WE is held at the low level has reached thedelay time τ₁ of the delay circuit 7. That is, the NOR gate circuit G₃provides a signal changing from the low level to the high level at atime t₅ at which the period of time τ₁ has lapsed from the time t₄. TheR-S flip-flop circuit 9 is set by the output signal of the NOR gatecircuit G₃ at the time t₅, and puts the write enabling signal WE" at itsinverting output terminal Q into the low level as shown at E in FIG. 5.

The output signal of the delay circuit 8 is made the high level at atime t₆ at which its delay time τ₂ has lapsed from the time t₅. As aresult, the R-S flip-flop circuit 9 is reset, and the write enablingsignal WE" at its inverting output terminal Q is made the high levelagain as shown at E in FIG. 5.

Accordingly, the gate circuits G₁ and G₂ carry out the writing operationfor the period of time τ₂ from the time after the time delay τ₁ withrespect to the write enabling signal WE externally supplied.

At a time t₇ after the writing operation has ended, the address signalA_(i) is altered so as to select a new memory cell, whereupon theoperation of reading or writing an information is executed likewise tothe above.

In the bipolar circuit having the current switching type memory cells asdescribed above, the minimum time t_(w) required for writing aninformation into any desired memory cell, in other words, the minimumpulse width required in the write enabling signal WE" changes dependingupon the setup time t_(WSA) of the write enabling signal WE" for theaddress signal A_(i) as illustrated by a characteristic curve A in FIG.6. Accordingly, the duration of the low level in the write enablingsignal WE" needs to be set greater than the writing time t_(w).

According to this embodiment, the low level duration of the writeenabling signal WE" to be supplied to the gate circuits G₁ and G₂ isdetermined by the delay circuit 8 within the pulse generator 6 and isnot affected by the period of the external write enabling signal WE.

The low level duration of the write enabling signal WE to be externallysupplied can be shortened down to a period required for the starting ofthe pulse generator 6, i.e., a period somewhat exceeding the delay timeτ₁ without being limited by the writing time t_(w). On the other hand,the write enabling signal WE" is internally formed as described above,so that the write enabling signal WE to be externally supplied can haveits back edge a delayed till the back edge b' of the address signalA_(i). Accordingly, the write enabling signal WE to be externallysupplied can have its timing margin made large.

The maximum pulse width of the write enabling signal as is determinedunder the condition that the writing of an information does not occur inany memory cell in the memory array, that is, the not-write pulse widtht_(nwp) changes depending upon the period of time from the setting ofthe address signal to the setting of the write signal, i.e., the setuptime t_(WSA) and becomes the minimum under a predetermined setup time tas illustrated by a curve B in FIG. 6. The fact that the not-write pulsewidth is small as at the setup time t signifies that, in case where apulse noise exceeding a logic threshold voltage has interfered in thewrite enabling signal, the resultant signal is regarded as the writeenabling signal, so an information is erroneously written into thememory cell.

In accordance with this embodiment, the pulse generator 6 is constructedso as to be started for the first time by a signal of a pulse widthexceeding the predetermined time τ₁. Therefore, even when a pulse noiseexists in the write enabling signal WE to be externally supplied, it isignored by the pulse generator 6. That is, since the gate circuits G₁and G₂ do not respond to external noise, any erroneous writing operationdoes not take place.

In case where, in contrast to this embodiment, the pulse generator asabove described is not disposed, in other words, the write enablingsignal WE externally supplied is applied to the gate circuits G₁ and G₂directly through the buffer circuit B₃, the setup time t_(WSA) of thewrite enabling signal relative to the address signal must be madegreater than a predetermined value in order that the not-write pulsewidth t_(nwp) may have a magnitude greater than a predetermined value.

In accordance with this embodiment, the write enabling signal WE" to beinternally formed is delayed the delay time τ₁ of the pulse generator 6with respect to the write enabling signal WE to be externally suppliedas described before. By making the delay time τ₁ substantially equal tothe required setup time, the time difference from the back edge b of theaddress signal A_(i) to the front edge a' of the external write enablingsignal WE can be reduced down to zero. As a result, the timing margin ofthe external write enabling signal WE can be made large.

In this embodiment, the write cycle can be made higher in speed for thereasons described previously and mentioned above.

With the construction as in the embodiment wherein the operation of theoutput buffer circuit B₁ is controlled by the write enabling signal andwherein the operating timing of the output buffer circuit B₁ is madedifferent from those of the gate circuits G₁ and G₂, the followingeffects can be achieved.

For example, in case where a comparatively heavy terminating resistorR_(L) is connected through the external terminal D_(out) to the outputend of the output buffer circuit B₁ constructed as shown in FIG. 4, anoperating current to flow through the output buffer circuit B₁ differsgreatly between the high level and low level of the output of thecircuit. By way of example, the operating current of the output buffercircuit for producing the output of the high level becomes a large valueof about 22 mA, while the operating current for producing the output ofthe low level becomes a small value of about 6 mA.

According to the construction of FIG. 1, when the memory circuit is notin the writing operation, the output buffer circuit B₁ provides a signalwhich corresponds to the stored information of a memory cell selected bythe address signal A_(i). When the external write enabling signal WE ismade by the low level, the output of the output buffer circuit B₁ isforced into the low level irrespective of the signals supplied to thesense lines S₁ and S₂.

Accordingly, when the write enabling signal WE is made the low level ata time t₁₀ as illustrated at D in FIG. 5 by way of example, the outputbuffer circuit B₁ has its output changed from the high level to the lowlevel at substantially the same time t₁₁ as the time t₁₀. As a result,the operating current of the output buffer circuit B₁ changes greatly.

Across the inductance component and resistance component (not shown) ofthe power supply line, for example, grounded interconnection GND of thememory circuit, a voltage is generated in response to the great changeof the operating current. Therefore, the potential of the groundedinterconnection GND is changed as shown at I in FIG. 5.

Unless the pulse generator 6 as previously stated is disposed, thepotential of the power supply line as above stated is changed by theoutput buffer circuit B₁ at substantially the same times as the frontedges of the write pulses W₀ and W₁. In this case, the changing timingsand changing levels of the write pulses W₀ and W₁ are unfavorablymodulated in response to the potential fluctuations of the power supplyline on account of the construction of the gate circuits G₁ and G₂. Asthe result of the impertinent changing timing and changing level of thewrite pulse, there arises the fear that an erroneous information will bewritten into the memory cell. Since, with the embodiment, the writingoperation is delayed the delay time τ₁ owing to the delay circuit 7relative to the external write enabling signal, the fluctuation timingof the power supply line can be brought into disagreement with the frontedges of the write pulses W₀ and W₁ (writing operation-startingtimings). It is accordingly possible to perform the writing operationunder a stable supply voltage state.

To the end of reducing the fluctuations of the potential on the powersupply line, an embodiment in FIG. 7 intends to supply the writeenabling signal provided from the buffer circuit B₃, to the outputbuffer circuit B₁ through an integration circuit 10.

Since the rates of change of the rise and fall of the control signal ofthe buffer circuit B₁ can be made small in this way, the voltagefluctuations of the power supply line GND can be made small. As aresult, even in case where the fluctuation timing of the power supplyline GND and the rise timing of the writing pulse W₁ are synchronous, astable writing operation is permitted.

The control signal WE of the output buffer circuit B₁ may well have therate of change of its rise or fall reduced by, for example, lowering theoutput driving capability of the input buffer circuit B₃ which formsthis signal WE.

This invention is not restricted to the foregoing embodiments, but thepulse generator 6 can be modified variously, and a NAND gate circuitetc. may well be adopted as the gate circuit G₃ in some ways of settinglogic levels. The flip-flop circuit 9 and the delay circuit 8 may wellbe replaced with a one-shot multivibrator.

As shown in FIG. 8, the write enabling signal to be supplied to thepulse generator 6 may well be generated from a logic circuit which isconstructed of resistors R₇ to R₉, transistors Q₂₀ to Q₂₃ and referencevoltage sources E₂ and E₃ and which receives the chip select signal CSand the write enabling signal WE.

In FIG. 8, transistors Q₂₅ and Q₂₆ have their bases brought into apotential higher than a reference potential E₄ and are therefore putinto the "on" state at the operation of reading an information.Transistors Q₂₇ and Q₂₈ are put into the "off" state accordingly. One oftransistors Q₂₉ and Q₃₀ is put into the "on" state by the input datasignal D_(in). The current of the transistor Q₂₉ or Q₃₀ flows to aresistor R₁₀ through the transistor Q₂₅ or Q₂₆. Since the transistorsQ₂₇ and Q₂₈ are held in the "off" state as described above,substantially no voltage drop occurs across resistors R₁₁ and R₁₂. As aresult, the potentials of the write lines W₁ and W₀ are made the samepotential as V_(R).

At the writing operation, the transistors Q₂₅ and Q₂₆ are put into the"off" state. At this time, if e.g. the input data signal D_(in) is atthe high level, the transistor Q₂₉ is in the "on" state and thetransistor Q₃₀ in the "off" state. Since the current of the transistorQ₂₉ flows to the resistors R₁₀ and R₁₂ through the transistor Q₂₈, thewrite line W₁ is made the low potential V_(WL) and the write line W₀ ismade the intermediate potential V_(R).

The control signal for the output buffer circuit is provided from a linel connected to the resistor R₇.

We claim:
 1. A bipolar memory circuit comprising:a plurality of memorycells, an address decoder which receives an address signal and whichprovides a signal for selecting one of the plurality of memory cellscorresponding to the address signal, a pulse generator which is startedby a write enabling signal and which provides a pulse signal having afixed pulse duration, and a gate circuit which receives an input datasignal and the pulse signal and which provides a write pulse signalcorresponding to the input data signal to be written into the selectedmemory cell, for a period determined by said pulse signal.
 2. A bipolarmemory circuit according to claim 1, wherein said pulse generator isconstructed of a first delay circuit which receives said write enablingsignal, a gate circuit which receives said write enabling signal and anoutput signal of said first delay circuit, and a first circuit which isstarted by an output signal of said gate circuit and which provides saidpulse signal having the fixed pulse duration.
 3. A bipolar memorycircuit according to claim 2, wherein said first circuit is constructedof a second delay circuit which receives said output signal of said gatecircuit, and a flip-flop circuit which has first and second stablestatuses, which is brought into the first stable status by said outputsignal of said gate circuit and which is brought into the second stablestatus by an output signal of said second delay circuit.
 4. A bipolarmemory circuit according to claim 1, further comprising a logic circuitwhich receives said write enabling signal and a chip enabling signal,said pulse generator being started by an output signal of said logiccircuit.
 5. A bipolar memory circuit according to claim 2, furthercomprising an output buffer circuit which receives a signal providedfrom the selected memory cell, said output buffer circuit having itsoperation controlled by said write enabling signal.
 6. A bipolar memorycircuit comprising:a plurality of memory cells, an address decoder whichreceives an address signal and which provides a signal for selecting oneof the plurality of memory cells corresponding to the address signal, apulse generator which receives a write enabling signal and whichprovides a pulse signal corresponding to the write enabling signal, agate circuit which receives an input data signal and the pulse signaland which provides a write pulse signal corresponding to the input datasignal to be written into the selected memory cell, for a perioddetermined by said pulse signal, an output buffer circuit which receivesa signal provided from the selected memory cell and a control signalwhich provides a signal corresponding to the signal provided from thememory cell, for a period determined by the control signal, and a delaycircuit which forms an output signal delayed with respect to an inputsignal thereof, an operating timing of said pulse generator and that ofsaid output buffer circuit being made different from each other by saiddelay circuit.
 7. A bipolar memory circuit according to claim 6, whereinthe control signal to be supplied to said output buffer circuit has itschanging rate limited by an integration circuit.
 8. A bipolar memorycircuit according to claim 6, said bipolar memory circuit being operatedby a single power supply.